A Programmable Resolution A/d Converter Modeling

This paper describes a VHDL implementation of a behavioural model for novel programmable resolution analog to digital converters (ADCs). This architecture uses the dichotomic method in the conversion. The goal for using this VHDL description is to validate the algorithm conversion and facilitate the synthesis of the digital part. In this example it includes digital control of dichotomic method. The structure of the converter is composed of a reference voltage generator, a programmable gain amplifier and a low resolution ADC. An ADC of 12-bits has been modeled and simulated using VHDL. The Static Test Ramp Method is applied for the testing of the 12bits ADC models. Also, we show how the analog parts affect the linearity of ADC. Static parameters such as INL and DNL are determined and presented.